The present invention relates to a transistor of SiC for high voltage and high switching frequency applications having an insulated gate and being one of a) a MISFET and b) an IGBT, the transistor comprising, superimposed on each other in the following order: a drain; a highly doped substrate layer being for a) of n-type and for b) of p-type, for b) on top thereof one of c) a highly doped n-type buffer layer and d) no such layer; and a low doped n-type drift layer; the transistor further comprising a plurality of laterally spaced unit cells each having a highly doped n-type source region layer, a source arranged on top of the source region layer, a p-type channel region layer separating the source region layer from the drift layer, an insulating layer located next to the channel region layer and extending from the source region layer to the drift layer and to the channel region layer and the source region layer of an adjacent unit cell and a gate electrode arranged on the insulating layer and adapted to form a conducting inversion channel extending in the channel region layer at the interface to the insulating layer for electron transport from the source to the drain upon applying a voltage thereto, the center to center distance of two adjacent unit cells defining a lateral width of a unit cell of the transistor.
The accumulation region is defined for instance by Baliga in "Modern Power Devices" (John Wiley & Sons, Inc, 1996) on page 369. In Si transistors having an insulated gate, such as MOSFETs, the design is mainly directed towards achieving as low specific on-resistance as possible, since power losses emanating from switching are almost neglectable with respect to the on-state conducting loses in the case of the relatively low blocking voltages in such devices of Si. Furthermore, the high on-resistance in Si devices is the main obstacle in realizing devices for higher voltages. For this reason, it is most frequently a desire to keep the cell pitch, i.e. the center to center distance of two adjacent unit cells, as small as possible in order to increase the packing density and thus reduce the on-resistance. This is possible to do in the trench type of devices without other than technological limitations but in the DMOS type of devices the on-state voltage increases again as the cells are put too close together due to the so called JFET effect which is the increase in vertical resistivity between the adjacent p-base regions belonging to the neighboring cells. For a determined lateral cell width it is also aimed at having an accumulation region with a lateral width being as large as possible, since it is understood that the on-state voltage does decrease with increasing ratio of accumulation region width to the total cell width.
Gate-controlled transistors, such as MOSFETs, of SiC have the operating potential at much higher voltages than those of Si. This is mainly due to much lower specific on-resistance of the drift region for a given voltage (200 times lower for 1 kV devices) compared to Si. However, with increasing voltage the importance of the switching losses increases. The switching losses in gate-controlled transistors of SiC have to be considered in a new and more careful way than what was the case so far, especially for high voltage and high switching frequency applications, since the power losses relating to the switching may otherwise strongly limit the performance and the applicability of such a semiconductor device.